1. Field of the Invention
The invention relates to controllers such as Serial ATA (SATA) host controllers. More particularly, the invention relates to enhanced controllers that reduce data transfer tasks of the host and the host memory to reduce the amount of data transfer on the interface between the host and the controller.
2. Description of the Related Art
Within the world of computers and computer architecture, data storage devices and their interfaces have become more sophisticated in their manufacture and operation, thus resulting in increased rates of data transfer and storage. The rate at which data is transferred between devices such as computer hard disks and drives such as Compact Disc Read/Write (CD-RW) drives is increasing proportionately greater than the increase in cycle time (clock speed) of the memory of the host computer. For example, data storage devices using the disk drive interface standard known as Advanced Technology Attachment (ATA), also known as Integrated Drive Electronics (IDE), currently have transfer rates of at least 2.4 Gigabits per second (Gb/s). The ATA standard, which has evolved into the standard known as Serial ATA (SATA or S-ATA), is characterized by the integration of the device controller on the device itself.
Data transfer between devices typically involves the transfer of data from a first device to the host memory, and then the transfer of data from the host memory to a second device. Data storage devices connect to the host computer by interfacing with a controller, e.g., a host controller, usually via an interface cable such as an IDE cable. The controller, e.g., an ATA controller or an SATA controller, interfaces with the host computer and its memory via a bus, e.g., a PCI bus or a PCI Express bus. A PCI bus is an interface bus manufactured and operated according to the Peripheral Component Interconnect (PCI) bus standard.
Accessing data from data storage devices at the relatively high data transfer rates mentioned above puts a load on the host, the host memory, and the bus connecting the host to the controller. Moreover, other devices and their interfaces, e.g., Universal Serial Bus (USB) and Firewire interfaces, compete for data transfer time on the bus connected to the host and the host memory.
Accordingly, it would be desirable to have an improved controller apparatus and method that reduce the use of the host, the host memory and the bus between the host and the controller during data transfer operations by offloading tasks conventionally required of the host, the host memory and the bus between the host and the controller.